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featur es ? 48.0 v input (36.0 v to 75.0 v), non-isolated zvs buck-boost regulator ? 20.0 v to 55.0 v adjustable output range ? 200 w output power in 0.57 in 2 footprint ? 96.7% typical efficiency, at full load ? 1341 w/in 3 (82 w/cm 3 ) power density ? 5.29 mhrs mtbf (mil-hdbk-217 plus parts count) ? pin selectable operating mode adaptive loop remote sense / slave ? half vi chip ? package 22.0mm x 16.5mm x 6.73mm t ypical applications ? high density power supply dc-dc rail outputs ? high density ate system dc-dc power ? telecom npu and asic core power ? communications systems ? non-isolated and isolated power converters pr oduct description the vi chip? prm tm regula t or is high eciency converter, oper a ting fr om a 36.0 t o 75.0 vdc input t o gener a t e a r egula t ed 20.0 t o 55.0 vdc output . the zvs buck-boost t opolog y enables h g i h h t i w n o i t a r e p o ) z h m 3 0 . 1 ~ ( y c n e u q e r f g n i h c t i w s h g i h conv er sion e ciency . high swit ching fr equency r educes the size of r eactiv e components enabling po w er densit y up t o 1341 w/in 3 . the half vi chip? package is compa tible with standar d pick- and-place and surface mount assembly pr ocesses with a planar thermal int erface ar ea and superior thermal conductivit y . in a f act orized pow er ar chit ectur e? sy st em, the prm and do wnstr eam vtm tm curr ent multiplier minimize distribution and conv er sion losses in a high po w er solution, pr o viding an isola t ed, r egula t ed output v oltage. the PRM48AH480X200A00 has tw o selectable modes of r egula tion depending on the applica tion r equir ements. in adaptiv e loop oper a tion, the prm48ah480 x200a00 utilizes a unique feed-forw ar d scheme tha t enables pr ecise r egula tion of an isola t ed pol v oltage without the need for r emot e sensing and v oltage feedback. in r emot e sense oper a tion, the int ernal r egula tion cir cuitry is disabled, and an e xt ernal contr ol loop and curr ent sensor maintain r egula tion. this a or ds ?e xibilit y in the design of both v oltage and curr ent compensa tion loops t o optimize performance in the end applica tion. prm tm regulator rev 1.5 page 1 of 42 11/2015 vicorpower.com 800 927.9474 high efficiency converter s n r t l c u s prm tm regulator 0 0 a 0 0 2 x 0 8 4 h a 8 4 m r p pr oduct ratings v in = 36.0 v to 75.0 v p out = 200 w v out = 48.0 v i out = 4.17 a (20.0 v to 55.0 v t rim)
rev 1.5 prm tm regulator page 2 of 42 11/2015 vicorpower.com 800 927.9474 PRM48AH480X200A00 prm enable trim share/ control node al ifb vc vt vaux ref/ ref_en +in Cn +out Cut tm vc pc v out +in Cn Cut +out adaptive loop t emperature feedback vtm start up pulse sgnd sgnd gnd sgnd r trim on/off control sgnd vf: 20 v to 55 v isolation bound ry sec_gnd vtm primary secondary c in c f c out vin l f r al external current sense gnd sgnd on/off control sgnd sgnd gnd voltage reference with soft start voltage sense and error amplifier (differential) vtm start up pulse sgnd in out gnd v ref v + vout Cn +in v C prm enable trim share/ control node al ifb vc vt vaux ref/ ref_en +in Cn +out Cut sgnd sgnd tm vc pc +in Cn Cut +out isolation boundry vtm primary secondary c in c f c out ref 3312 [1] [1] v in l f sgnd voltage sense sgnd load $b92,*59952,*=287< [1] non-isolated con?guration: Cout connected to -in typical application: PRM48AH480X200A00 + vtm, non-isolated remote sense configuration typical application: PRM48AH480X200A00 + vtm adaptive loop configuration
rev 1.5 prm tm regulator page 3 of 42 11/2015 vicorpower.com 800 927.9474 PRM48AH480X200A00 half vic 1 2 3 4 a b c d e f g h a b c d e f g h share/ control node enable trim nc nc al vt vaux ifb sgnd ref/ref_en vc +in -in +out -out top view !27 >6+.; #207*5*6. $b9. >7,=287 share a1 (adaptive loop / slave operation) bidir parallel sharing control bus for master-slave con?guration. control node modulator control node input. driven by external error ampli?er in remote sense (remote sense operation) input operation. a3 vt input vtm tm input for temperature compensation. leave disconnected for remote sense (adaptive loop operation) operation. b2 enable bidir enables power supply when allowed to ?oat high. 5 v during normal operation. b4 vaux output 9 v auxiliary bias voltage. c1 trim input selects operating mode. adjusts output voltage in adaptive loop operation. c3 ifb input current sense input for current limit and overcurrent protection in remote sense operation. (remote sense operation) leave disconnected for adaptive loop operation. d2 nc n/a do not connect this pin. d4 sgnd input signal ground, reference for analog controls. kelvin connected internally to Cin and Cout. e1 nc n/a do not connect this pin. ref e3 (adaptive loop operation) output reference voltage for internal error ampli?er in adaptive loop operation. ref_en (remote sense operation) output powers and enables external control circuit voltage reference in remote sense operation. f2 al input adaptive loop gain control. sets the magnitude of the adaptive loop load line in adaptive (adaptive loop operation) loop operation. leave disconnected for remote sense operation. f4 vc output bias voltage to power vtm module during start up g1,g2 +in input positive input power terminal power g3,g4 +out output positive output power terminal power h1,h2 -in input negative input power terminal. connected internally to -out. power return h3,h4 -out output negative output power terminal. connected internally to -in. power return pin con?guration pin descriptions
rev 1.5 prm tm regulator page 4 of 42 11/2015 vicorpower.com 800 927.9474 PRM48AH480X200A00 device input voltage range package type output voltage x 10 temperature grade output power revision version prm 48a h 480 t 200 a 00 prm = prm 48a = 36.0 v - 75.0 v h = half vic 480 = 48.0 v t = -40 to 125c 200 = 200 wa 00 = al / rs smd m = -55 to 125c part ordering information part number v in package type v out temperature power version prm48ah480 t 200a00 36.0 v - 75.0 v half vic 48.0 v -40 to 125c 200 w al / rs prm48ah480 m 200a00 smd (20.0 v to 55.0 v) -55 to 125c (pin selectable) standard models parameter comments min max unit share / control node -0.3 10.5 v +/-10 ma enable -0.3 5.5 v +/-10 ma +in to Cin continuous, non-operating -1 90 v 100 ms, non-operating 100 v vaux -0.5 10.5 v +/-100 ma sgnd +/-100 ma ifb -0.5 5.7 v -0.3 3.6 v ref / ref _en remote sense operation (ref _en) 10 ma adaptive loop operation (ref) 3.4 ma trim -0.3 3.6 v al -0.3 3.6 v vt -0.3 4.8 v vc to Cout -0.5 18 v +/-1.8 a +out to Cout -1 62 v output current 6.3 a internal operating t grade -40 125 c temperature m grade -55 125 c storage t grade -40 125 c temperature m grade -65 125 c absolute maximum ratings the absolute maximum ratings below are stress ratings only. operation at or beyond these maximum ratings can cause permanent damage to device. electrical specifications do not apply when operating beyond rated operating conditions. operating beyond rated operating conditions for extended period of time may affect device reliability. all voltages are specified relative to sgnd unless otherwise noted. positive pin current represents current flowing out of the pin.
rev 1.5 prm tm regulator page 5 of 42 11/2015 vicorpower.com 800 927.9474 PRM48AH480X200A00 electrical speci?cations specifications apply over all line and load conditions, and trim from 20.0 v to 55.0 v, unless otherwise noted; boldface specifications apply over the temperature range of -40oc < t int < 125oc; all other specifications are at t int = 25oc unless otherwise noted. attribute symbol conditions / notes min typ max unit power input speci?cation input voltage range v in continuous, operating 36.0 48.0 75.0 v v in slew rate dv in /dt 0 v in 75.0 v 0.001 1000 v/ms initialization voltage v init internal micro controller initialization voltage 10 v initialization delay t init from v in ?rst crossing v init 5.0 7.0 9.0 ms no load power dissipation p nl enable high, v in = 48.0 v 2.4 3.5 w input quiescent current i qc enable low, v in = 48.0 v 14.5 20.0 ma input current i in_dc i out = 4.17 a, v in = 48.0 v, v out = 48.0 v 4.3 4.4 a input capacitance (internal) c in_int effective value, v in = 48.0 v (see fig. 13)2 f input capacitance (internal) esr r cin effective value, v in = 48.0 v 3.0 m? power output speci?cation rated output current i out standalone and master operation, see figure 1, soa 4.17 a rated output power p out standalone and master operation, see figure 1, soa 200 w v in = 48.0 v v out = 48.0 v, switching frequency f sw i out = 2.08 a, t int = 25c 0.94 1.03 1.07 mhz over line, load, trim and temperature, 0.70 1.07 mhz exclusive of burst mode from v in ?rst crossing v in_uvlo+_supv 20 s output turn-on delay t on to enable high; t init expired from enable pin release to enable high, v in applied, t off expired 20 s start up sequence timeout t startup_seq from enable high to start up sequence complete 17 ms v in = 48.0 v, v out = 48.0 v, i out = 4.17 a, t int = 25c 95.25 % v in = 48.0 v, v out = 48.0 v, i out = 2.08 a, t int = 25c 94.0 95.0 % ef?ciency ambient amb v in = 36.0 v to 75.0 v, 93.25 % v out = 48.0 v, i out = 4.17 a, t int = 25c v in = 36.0 v to 75.0 v, i out = 4.17 a, t int = 25c, over trim 90.0 % v in = 48.0 v, v out = 48.0 v, i out = 4.17 a, t int = 100c 94.8 96.8 % v in = 48.0 v, v out = 48.0 v, i out = 2.08 a, t int = 100c 94.0 96.0 % ef?ciency hot hot v in = 36.0 v to 75.0 v , v out = 48.0 v, i out = 4.17 a, t int = 100c 93.5 % v in = 36.0 v to 75.0 v , i out = 4.17 a, t int = 100c, over trim 90.0 % ef?ciency over temperature >50% load and v out = 48.0 v; over temperature 94.0 % >50% load; over temperature and trim 87.0 % output discharge current i od average value 0.5 ma output voltage ripple v out_pp v in = 48.0 v, v out = 48.0 v, i out = 4.17 a, c out_ext = 0 f, 20 mhz bw 1000 1500 mv output inductance (parasitic) l out_par frequency @ 1.03 mhz, simulated j-lead model 2.5 nh output capacitance (internal) c out_int effective value, v out = 48.0 v (see fig. 13)2 f output capacitance (internal) esr r cout effective value, v out = 48.0 v 3.0 m?
rev 1.5 prm tm regulator page 6 of 42 11/2015 vicorpower.com 800 927.9474 PRM48AH480X200A00 electrical speci?cations (cont.) specifications apply over all line and load conditions, and trim from 20.0 v to 55.0 v, unless otherwise noted; boldface specifications apply over the temperature range of -40oc < t int < 125oc; all other specifications are at t int = 25oc unless otherwise noted. attribute symbol conditions / notes min typ max unit power output speci?cations: adaptive loop operation output voltage setpoint v out_set no load, trim inactive, adaptive loop load line inactive 47.00 48.00 49.00 v output voltage trim range v out 20.0 55.0 v output voltage rise time t rise_vout from soft start initiated to output voltage settled 1.7 1.8 1.9 ms output voltage load regulation v out_reg_load adaptive loop load line inactive 0.02 0.2 % output voltage line regulation v out_reg_line adaptive loop load line inactive 0.02 0.2 % total regulation error v out_reg_total prm output voltage, adaptive loop load line inactive 0.2 % vtm output voltage, total adaptive loop regulation, 1 3 % total al regulation error v out_reg_al v out = 48.0 v, trim inactive vtm output voltage, total adaptive loop regulation, 5 % trim active, exclusive of external resistor tolerances v in = 48.0 v, v out = 48.0 v, t int = 25c, constant 4.6 5.2 5.8 a output current limit i limit current limit after supervisory limit detection time t lim_supv over line, load, trim and temperature 4.2 6.3 a load capacitance (electrolytic) c load_alel 0.1 ? esr 1 ? , see figure 32, total capacitance (c load_alel + c load_cer ) 47 f 47 f load capacitance (ceramic) c load_cer 2m ? esr 200 m ? , see figure 32 25 f load transient voltage deviation v trans 10% ? 100% load step, 10 a/sec, 0 f c out , 4.8 v deviation from initial setpoint 10% ? 100% load step, 10 a/sec, 0 f c out , recovery to 90% of final value, adaptive loop 100 s load transient recovery time t trans load line inactive 10% ? 100% load step, 10 a/sec, 0 f c out , recovery to 90% of final value, 500 s adaptive loop load line active, v al = 1.20 v power output speci?cations: slave operation with al master slave operation within an array, up to 5c case 3.3 a rated current within an array i out_array temperature differential, master-slave con?guration slave operation within an array, up to 30c case 2.9 a temperature differential, master-slave con?guration slave operation within an array, up to 5c case 160 w rated power within an array p out_array temperature differential, master-slave con?guration slave operation within an array, up to 30c case 140 w temperature differential, master-slave con?guration equal input, and output voltage at full load; 15 % v in = 48.0 v, v out = 48.0 v equal input and output voltage at full load; current sharing difference i out_share_ms over line and trim, with 25c t c 100c and 5c 15 % (master to slave) part-part temp. mismatch equal input, and output voltage at full load; over line and trim, with 25c t c 100c 20 % and 30c part-part temp. mismatch
rev 1.5 prm tm regulator page 7 of 42 11/2015 vicorpower.com 800 927.9474 PRM48AH480X200A00 electrical speci?cations (cont.) specifications apply over all line and load conditions, and trim from 20.0 v to 55.0 v, unless otherwise noted; boldface specifications apply over the temperature range of -40oc < t int < 125oc; all other specifications are at t int = 25oc unless otherwise noted. attribute symbol conditions / notes min typ max unit power output speci?cations: slave operations (cont.) equal input, output, and share voltage at full load; v in = 48.0 v, v out = 48.0 v 5 % equal input, output and share voltage at full load; current sharing difference i out_share_ss over line and trim, with 25c t c 100c 10 % (slave to slave) and 5c part-part temp. mismatch equal input, output, and share voltage at full load; over line and trim, with 25c t c 100c 15 % and 30c part-part temp. mismatch maximum array size n prms_parallel maximum number of parallel devices, 5 prms master-slave con?guration power output speci?cations: remote sense operation output voltage range v out 20.0 55.0 v remote sense operation within an array, 3.8 a rated current within an array i out_array up to 5c case temperature differential remote sense operation within an array, 3.3 a up to 30c case temperature differential remote sense operation within an array, 180 w rated power within an array p out_array up to 5c case temperature differential remote sense operation within an array, 160 w up to 30c case temperature differential equal input, output, and control node voltage 5 % at full load; v in = 48.0 v, v out = 48.0 v equal input, output and control node voltage at full load; over line and trim, with 25c t c 100c 10 % current sharing difference i out_share_rs and 5c part-part temp. mismatch equal input, output, and control node voltage at full load; over line and trim, 15 % with 25c t c 100c and 30c part-part temp. mismatch (worst case) maximum array size n prms_parallel maximum number of parallel devices, remote sense 10 prms con?guration, control node externally driven
rev 1.5 prm tm regulator page 8 of 42 11/2015 vicorpower.com 800 927.9474 PRM48AH480X200A00 electrical speci?cations (cont.) specifications apply over all line and load conditions, and trim from 20.0 v to 55.0 v, unless otherwise noted; boldface specifications apply over the temperature range of -40oc < t int < 125oc; all other specifications are at t int = 25oc unless otherwise noted. attribute symbol conditions / notes min typ max unit powertrain protections input undervoltage turn-on v in_uvlo+ 30.9 33.0 v input undervoltage turn-off v in_uvlo- instantaneous powertrain shutdown, detected after t blank 26.0 28.8 v input undervoltage hysteresis v uvlo_hyst (v in_uvlo+ ) - (v in_uvlo- ) 1.9 2.2 2.4 v input overvoltage turn-on v in_ovlo- 79.6 82.9 v input overvoltage turn-off v in_ovlo+ instantaneous powertrain shutdown, detected after t blank 84.6 88.8 v input overvoltage hysteresis v ovlo_hyst (v in_ovlo+ ) - (v in_ovlo- ) 1.4 1.7 2.1 v output overvoltage threshold v out_ovp+ instantaneous shutdown, detected after t prot 56.0 58.3 60.1 v minimum current limited vout v out_uvp 12 v overtemperature shutdown setpoint t int_otp instantaneous shutdown, detected after t prot 125 oc output power limit p prot 200 w short circuit v out threshold v sc_vout 8.8 v short circuit v out recovery threshold v sc_voutr 9.5 v short circuit control node threshold v sc_vcn 7.2 v short circuit control node v sc_vcnr 6.9 v recovery threshold short circuit timeout t sc short circuit fault detected after v sc _ vout and v sc _ vcn thresholds persist for this time 5 ms short circuit recovery time t scr excludes t off 75 ms overcurrent (ifb) and t blank 50 120 150 s input over/undervoltage blanking time overtemperature, output overvoltage and enable shutdown response time t prot 2 s (hardware) powertrain supervisory limits input undervoltage turn-on v in_uvlo+_supv 33.8 35.2 v (supervisory) input undervoltage turn-off v in_uvlo-_supv powertrain shutdown, detected after t lim_supv 30.5 31.8 v (supervisory) input undervoltage hysteresis v uvlo_hyst_supv (v in_uvlo+_supv ) - (v in_uvlo-_supv ) 1.6 2.0 2.1 v (supervisory) input overvoltage turn-on v in_ovlo-_supv 75.6 78.8 v (supervisory) input overvoltage turn-off v in_ovlo+_supv powertrain shutdown, detected after t lim_supv 80.3 82.7 v (supervisory) input overvoltage hysteresis v ovlo_hyst_supv (v in_uvlo+_supv ) - (v in_uvlo-_supv ) 1.2 1.5 1.8 v (supervisory) undertemperature shutdown setpoint t int_utp t grade -40 oc (supervisory) m grade -55 oc supervisory limit response time t lim_supv 150 s
rev 1.5 prm tm regulator page 9 of 42 11/2015 vicorpower.com 800 927.9474 PRM48AH480X200A00 enable ? the enable pin enables and disables the prm ? in prm array con?gurations, enable pins should be connected in order to synchronize start up ? enable is 5 v with 1.8 ma source capability during normal operation signal type state attribute symbol conditions / notes min typ max unit normal enable voltage v enable 4.7 5.0 5.3 v analog output operation enable current i enable_op 1.8 ma start up enable source current i enable_en after t off 90 a minimum time to start t off 13.0 15.0 17.0 ms start up enable v enable_en 2.5 3.2 v enable threshold enable v enable_dis 0.97 2.40 v digital input / output standby disable threshold enable r enable_ext resistance to sgnd required 235 ? resistance (external) to disable the prm digital output fault enable i enable_fault enable voltage 1 v or above 4 ma sink current to sgnd signal speci?cations specifications apply over all line and load conditions, t int = 25oc and output voltage from 20.0 v to 55.0 v, unless otherwise noted. boldface specifications apply over the temperature range of -40oc < t int < 125oc (t-grade). vaux: auxillary voltage source ? intended to power auxiliary circuits ? 9 v during normal operation with 5 ma source capability signal type state attribute symbol conditions / notes min typ max unit vaux voltage v vaux 8.6 9.0 9.5 v normal vaux current i vaux 5 ma operation i out = 0a, c vaux_ext = 0. maximum vaux voltage ripple v vaux_pp speci?cation includes powertrain 100 400 mv analog output operation in burst mode. vaux capacitance c vaux_ext 0.04 f transition (external) vaux fault response t fr_vaux from fault recognition to 30 s time vaux = 1.5 v vc: vtm control ? pulsed voltage source used to power and synchronize downstream vtm during start up ? 14 v, 10 ms typical voltage pulse signal type state attribute symbol conditions / notes min typ max unit vc voltage v vc_start connected to vtm vc or equivalent, 13 14 18 v i vc = 115 ma, c vc = 3.2 uf analog output start up vc available current i vc_start v c = 14 v, v in > 20 v 200 ma vc duration t vc 7 10 16 ms vc slew rate dvc/dt connected to vtm or equivalent, i vc = 115 ma, c vc = 3.2 uf 0.02 0.25 v/s enable to vc delay t enable-vc 20 s
rev 1.5 prm tm regulator page 10 of 42 11/2015 vicorpower.com 800 927.9474 PRM48AH480X200A00 sgnd: signal ground ? all control signals must be referenced to this pin, with the exception of vc ? sgnd is internally connected to -in and -out signal type state attribute symbol conditions / notes min typ max unit analog input / output any maximum allowable i sgnd -100 100 ma current signal speci?cations (cont.) specifications apply over all line and load conditions, t int = 25oc and output voltage from 20.0 v to 55.0 v, unless otherwise noted. boldface specifications apply over the temperature range of -40oc < t int < 125oc (t-grade). trim ? trim is used to select operating mode and trim the output voltage in adaptive loop operation ? internal pullup to v cc_int through 10 k ? resistor ? when pulled below 0.45 v during power up, remote sense / slave operation is selected ? when allowed to pull up above 0.55 v during power up, adaptive loop operation is selected ? operating mode is detected during power up and cannot be changed unless input power is cycled signal type state attribute symbol conditions / notes min typ max unit internally generated v cc_int 3.20 3.28 3.36 v normal vcc operation internal pullup r trim_int 0.5% tolerance resistor 9.83 10.00 10.18 k? resistance to v cc_int analog input mode detection t mode_detect from enable high to mode detected, 100 140 200 s delay after v in ?rst applied mode remote sense pull below this value during ?rst detect enable threshold v rs_mode_en start up after application of power to 0.45 v enable remote sense / slave operation remote sense pull above this value during ?rst disable threshold v rs_mode_dis start up after application of power to 0.55 v enable adaptive loop operation
rev 1.5 prm tm regulator page 11 of 42 11/2015 vicorpower.com 800 927.9474 PRM48AH480X200A00 signal speci?cations (cont.) specifications apply over all line and load conditions, t int = 25oc and output voltage from 20.0 v to 55.0 v, unless otherwise noted. boldface specifications apply over the temperature range of -40oc < t int < 125oc (t-grade). trim (adaptive loop operation only) ? provides dynamic trim control over the prm output voltage in adaptive loop operation ? sampled prior to every start up to detect if trim is active or inactive ? output voltage is equal to 20 times the voltage at the trim pin when applied trim voltage is within the active range ? trim state is detected during normal operation and cannot be changed until start up is initiated signal type state attribute symbol conditions / notes min typ max unit trim enable threshold v trim_en pull below this value during 3.10 v start up to enable trim control trim disable threshold v trim_dis pull above this value during start up to disable trim control 3.20 v start up minimum trim disable r trim_dis_min minimum trim resistance required 10 m? resistance to disable trim trim capacitance c trim_ext 100 pf (external) trim sample delay t enable_trim from enable high to trim sampled 100 140 200 s analog input trim pin v trim_range see figure 26 1.00 2.75 v analog range trim gain g trim v out / v trim , 20 v / v v trim applied within active range normal trim accuracy % acc_trim vout accuracy, exclusive of operation external resistor tolerance 0.5 2.0 % v out referred v out_res 200 mv trim resolution trim latency t trim_lat 60 120 240 s trim bandwidth bw trim -3db point 1.2 khz
rev 1.5 prm tm regulator page 12 of 42 11/2015 vicorpower.com 800 927.9474 PRM48AH480X200A00 al: adaptive loop (adaptive loop operation only) ? provides adaptive loop load line programming in adaptive loop operation ? internal pullup to v cc_int through 10 k ? resistor ? sampled prior to every start up to detect if adaptive loop load line is active or inactive ? leave open to disable adaptive loop load line ? not used in remote sense operation signal type state attribute symbol conditions / notes min typ max unit al enable threshold v al_en pull below this value during start up 3.10 v to enable al load line al disable threshold v al_dis pull above this value during start up 3.20 v to disable al load line start up minimum al disable r al_dis_min minimum al resistance required 10 m? resistance to disable al load line al capacitance c al_ext 100 pf (external) al sample delay t enable_al from enable high to al sampled 100 140 200 s internally generated v cc_int 3.20 3.28 3.36 v analog input vcc internal pullup r al_int 0.5 % tolerance resistor 9.83 10.00 10.18 k? resistance to v cc_int al pin analog range v al_range 0 3.10 v normal al gain g al positive correction slope, vt inactive 1.0 ? /v operation al load line accuracy % acc_ll_al full load slope accuracy exclusive 0.5 2.0 % of external resistor tolerance al load line resolution ll al_res 3m ? maximum output v out_al_max maximum increase from no 5 v referred compensation load setpoint, v out 55.0 v al latency t al_lat 60 120 240 s al bandwidth bw al -3db point 1.2 khz signal speci?cations (cont.) specifications apply over all line and load conditions, t int = 25oc and output voltage from 20.0 v to 55.0 v, unless otherwise noted. boldface specifications apply over the temperature range of -40oc < t int < 125oc (t-grade).
rev 1.5 prm tm regulator page 13 of 42 11/2015 vicorpower.com 800 927.9474 PRM48AH480X200A00 signal speci?cations (cont.) specifications apply over all line and load conditions, t int = 25oc and output voltage from 20.0 v to 55.0 v, unless otherwise noted. boldface specifications apply over the temperature range of -40oc < t int < 125oc (t-grade). ref: reference (adaptive loop operation only) ? functions as ref pin in adaptive loop operation ? ref represents the internal voltage reference for the voltage control circuit ? v out approximately equal to 20 times ref voltage signal type state attribute symbol conditions / notes min typ max unit ref voltage v ref v out = 48.0 v, trim inactive 2.4 v ref to v out g ref_vout v out / v ref 20 v / v normal scale factor operation ref resistance r ref_ext 10 m? analog output (external) ref capacitance c ref_ext 200 pf (external) ref voltage ripple v ref_pp includes burst mode, 20 mhz bw 25 mv enable to ref delay t enable_ref enable low to ref low 120 s transition vaux to ref delay t vaux_ref vaux = 8.1 v to ref soft start ramp initiated 1 ms vt: vtm temperature (adaptive loop operation only) ? vtm temperature compensation for adaptive loop regulation ? adjusts the slope of the adaptive loop load line to account for changes in vtm output resistance over temperature ? connect to tm pin of compatible downstream vtm to enable temperature compensation ? leave disconnected to disable temperature compensation signal type state attribute symbol conditions / notes min typ max unit internal resistance r vt_int 80.0 k? to sgnd vt enable threshold v vt_en 2.1 v vt disable threshold v vt_dis pull below this value to disable vt 1.9 v temperature compensation vt disable default t vt_dis default al temperature setting analog input normal temperature when vt disabled 25 c operation vt analog range v vt_op 2.18 3.98 v tc vt vt within active range, referenced 30 %/v vt temperature to 2.98 v coef?cient tc vt vtm tm voltage applied, .01v/k, referenced to 25c 0.3 %/c vt resolution tc vt_res vtm tm voltage applied, .01v/k 0.4 c vt latency t vt_lat 60 120 240 s bandwidth bw vt -3db point 1.5 khz
rev 1.5 prm tm regulator page 14 of 42 11/2015 vicorpower.com 800 927.9474 PRM48AH480X200A00 signal speci?cations (cont.) specifications apply over all line and load conditions, t int = 25oc and output voltage from 20.0 v to 55.0 v, unless otherwise noted. boldface specifications apply over the temperature range of -40oc < t int < 125oc (t-grade). share (adaptive loop and slave operation only) ? functions as share pin in master slave array con?guration ? current share bus for array operation (master/slave scheme) ? sources current and provides share signal in master operation ? sinks constant current when externally driven in active range (slave operation) signal type state attribute symbol conditions / notes min typ max unit share voltage v share 0.79 7.40 v standalone/ active range analog output master share available i share v share > 0.79 v 2.5 ma operation current share resistance r share 93.3 k? to sgnd slave share sink current i share_sink v share > 0.79 v 0.25 0.50 0.75 ma analog input operation ref_en: reference enable (remote sense and slave operation only) ? functions as ref_en pin in remote sense and slave operation ? ref_en signals successful start up and powertrain ready to operate ? intended to power and enable the external feedback circuit reference in remote sense operation ? 3.25 v, 4 ma regulated voltage source signal type state attribute symbol conditions / notes min typ max unit ref_en voltage v ref_en ref_en unloaded 2.72 3.25 3.37 v ref_en source r out_ref_en 50 100 ? impedance normal ref_en current i ref_en 4 ma analog output operation ref_en capacitance c ref_en_ext 0.1 f (external) ref_en voltage ripple v ref_en_pp includes burst mode, 20 mhz bw 25 mv enable to ref_en t enable_ref_en enable low to ref_en low 120 s transition delay vaux to ref_en t vaux_ref_en vaux = 8.1 v to ref_en high 1 ms delay
rev 1.5 prm tm regulator page 15 of 42 11/2015 vicorpower.com 800 927.9474 PRM48AH480X200A00 control node (remote sense operation only) ? functions as control node pin in remote sense operation ? modulator control node voltage sets power train timing ? driven by external error ampli?er in remote sense operation ? sinks constant current when externally driven in active range ? sources current, and clamps voltage to 0.79 v when pulled below active range signal type state attribute symbol conditions / notes min typ max unit control node v cn 0.79 7.40 v voltage active range control node i cn_low v cn < 0.79 v 2.5 ma analog input normal source current operation control node i cn_sink v cn > 0.79 v 0.25 0.50 0.75 ma sink current control node r cn 93.3 k? resistance to sgnd ifb: current feedback (remote sense operation only) ? functions as ifb pin in remote sense operation ? a voltage proportional to the prm output current must be supplied externally to the ifb pin in order for the device to properly protect overcurrent events and to enable output current limit (clamp) ? overcurrent protection trip will cause instantaneous powertrain disable, detected after t blank ? not used for adaptive loop operation signal type state attribute symbol conditions / notes min typ max unit current limit (clamp) v in = 48.0 v; v out = 48.0 v threshold v ifb_il t int = 25c 1.90 2.00 2.10 v over line, trim, and temperature 1.85 2.15 v not production tested; guaranteed analog input normal overcurrent by design; t int = 25c 2.58 2.69 2.80 v operation protection v ifb_oc not production tested; guaranteed threshold by design; over line, trim, 2.56 2.82 v and temperature ifb input impedance r ifb 2.09 2.13 2.17 k? current limit bw il 2.0 khz bandwidth signal speci?cations (cont.) specifications apply over all line and load conditions, t int = 25oc and output voltage from 20.0 v to 55.0 v, unless otherwise noted. boldface specifications apply over the temperature range of -40oc < t int < 125oc (t-grade). nc: no connect ? reserved for factory use only ? no connections should be made to these pins
rev 1.5 prm tm regulator page 16 of 42 11/2015 vicorpower.com 800 927.9474 PRM48AH480X200A00 functional block diagram +out -out l q1 q2 q3 c out +in -in c in q4 sh are/ control node 57.6 k ? 35.7 k ? 1000 pf en able trim 3.3 v 10 k? 1000 pf nc nc 10 k ? 0.01 uf al 20 60.4 vt 2200 pf vaux 0.01 uf 2.1 30.1k? ifb 0.01 uf ref/ ref_en 10 6800 pf otp 0.5 ma 2.5 ma min in out pgnd sgn d 1.58 30.1 vcc sgn d vc pgnd sgnd k? 10 k? 10 k? k? k? k? k? k? current limit adaptive loop output overvoltage protection undervoltage lockout overvoltage lockout output short circuit control and monitoring error amplifier voltage reference modulator enable internal vcc regulator 3.3 v linear regulator
rev 1.5 prm tm regulator page 17 of 42 11/2015 vicorpower.com 800 927.9474 PRM48AH480X200A00 high level functional state diagram conditions that cause state transitions are shown along arrows. sub-sequence activities listed inside the state bubbles. startup sequence t on expired enable: 1.8ma to high vc pulse ref_en active adaptive loop and trim modes latched rs mode latched at first enable after vin applied only powertrain active standby sequence enable: 10ua to low t off expired enable: 90ua to high powertrain stopped application of vin enable rising edge enable falling edge, output ovp or otp detected fault sequence enable pulsed: 25ma to low powertrain stopped v in > uvlo+ enable falling edge, output ovp, or otp detected t startup_seq expired sustained operation enable: 1.8ma to high powertrain active input ovlo or uvlo, output uvp, or utp detected short circuit detected input ovlo or uvlo, output uvp, or utp detected fault auto- recovery
rev 1.5 prm tm regulator page 18 of 42 11/2015 vicorpower.com 800 927.9474 PRM48AH480X200A00 timing diagrams (adaptive loop operation) module inputs are shown in blue; module outputs are shown in brown. ref v out enable share +in vc vaux trim iout v vc_start 3.3v 2.4v t vc t blank 1 input power on and uv turn on 3 al active 4 input ov 5 input ov recovery 6 enable disable 7 enable release 8 full load applied 9 output ov t off t on t on t blank t blank t aux_ref t prot t prot bidir bidir bidir output output output output input input al v init t off 1v 48v 55v 2.75v 1.0v 20v 0v 2 trim inactive al = 1v t enable_vc v in_ovlo v in_uvlo v share_max v share_min i limit v enable v enable_en v out_ovp+ v out_max v out_nom v out_min v aux t startup_seq al = 1v input v ref firstenb: tr not low = not rs mode tr high = trim inactive for this enabled period al not high = al active for this enabled period tr high = trim inactive for this enabled period al not high = al active for this enabled period tr high = trim inactive for this enabled period al not high = al active for this enabled period soft start trim ignored vout increases by v al * g al * i out trim and al pins sampled soft start micro controller initialized current sense activated, and output increase due to al after t startup_seq expires
rev 1.5 prm tm regulator page 19 of 42 11/2015 vicorpower.com 800 927.9474 PRM48AH480X200A00 ref v out enable share +in vc vaux trim iout v in_ovlo v enable_en v enable v vc_start v aux v share_min i limit v share_max 10 input power on and uv turn on 12 output short circuit 15 output power limit protection 16 current limit event 17 input power off and uv turn off t off t sc t blank 20v input bidir bidir bidir output output output output input input 2.75v al v init 1 v 3.3v 55v 2.4v 48v 1 v 2.4v 2.75v 3.3v 1v 14 ot shutdown and recovery 13 enable toggling 11 al inactive and trim active v out_max v out_min v out_nom v in_uvlo t startup_seq firstenb: tr not low = not rs mode tr not high = trim ac ve for this enabled period al high = al inac ve for this enabled period tr not high = trim ac ve for this enabled period al high = al inac ve for this enabled period tr high = trim inac ve for this enabled period al not high = al ac ve for this enabled period tr high = trim inac ve for this enabled period al not high = al ac ve for this enabled period t lim_supv t scr +t off t blank al pin ignored v out = v trim * 20 v out clamped to 55v for v trim > 2.75v al ac ve vout increase due to iout and al a!er t startup_seq expires opera ng mode trim and al state detected micro controller ini alized $262702*0;*6<-*9=2?.889 9.;*=287,87= module inputs are shown in blue; module outputs are shown in brown.
rev 1.5 prm tm regulator page 20 of 42 11/2015 vicorpower.com 800 927.9474 PRM48AH480X200A00 ref_en v out enable control node +in vc vaux trim ifb v enable_en v enable v vc_start v cn_max v aux v ref_en t vc v ifb_oc t blank 1 input power on and uv turn on t < t blank 2 quick oc (t rev 1.5 prm tm regulator page 21 of 42 11/2015 vicorpower.com 800 927.9474 PRM48AH480X200A00 ref_en v out enable control node +in vc vaux trim ifb 9 start up with minimum < dv in /dt < 1.2v/ms 10 output short circuit 11 output power limit protection 12 current limit event 13 input uv t off t sc rev 1.5 prm tm regulator page 22 of 42 11/2015 vicorpower.com 800 927.9474 PRM48AH480X200A00

! ! "#$ figure 2 no load power dissipation vs. v in , module enabled 20 25 30 35 40 45 50 55 60 output voltage (v) output current (a) dc safe operating area 0.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 225 200 175 150 125 100 75 50 25 current power output power (w) figure 1 dc safe operating area (soa)

figure 3 no load power dissipation vs. v in , module disabled - enable = low

!"#$# % !&'#( figure 4 total efficiency and power dissipation vs. v in and i out v out = 20.0 v, t case = -40c

!"#$# % !&##' figure 6 total efficiency and power dissipation vs. v in and i out v out = 20.0 v, t case = 100c

!"#$# % !"&' figure 5 total efficiency and power dissipation vs. v in and i out v out = 20.0 v, t case = 25c typical performance characteristics the following figures present typical performance at t c = 25oc, unless otherwise noted. see associated figures for general trend data.
rev 1.5 prm tm regulator page 23 of 42 11/2015 vicorpower.com 800 927.9474 PRM48AH480X200A00

!"#$% & !'() figure 8 total efficiency and power dissipation vs. v in and i out v out = 48.0 v, t case = 25c

!"#$% & !'"%( figure 7 total efficiency and power dissipation vs. v in and i out v out = 48.0 v, t case = -40c

!"#$% & !'%%( figure 9 total efficiency and power dissipation vs. v in and i out v out = 48.0 v, t case = 100c

!""#$ % !&'$( figure 10 total efficiency and power dissipation vs. v in and i out v out = 55.0 v, t case = -40c

!""#$ % !&$$' figure 12 total efficiency and power dissipation vs. v in and i out v out = 55.0 v, t case = 100c

!""#$ % !&"' figure 11 total efficiency and power dissipation vs. v in and i out v out = 55.0 v, t case = 25c typical performance characteristics (cont.) the following figures present typical performance at t c = 25oc, unless otherwise noted. see associated figures for general trend data.
rev 1.5 prm tm regulator page 24 of 42 11/2015 vicorpower.com 800 927.9474 PRM48AH480X200A00 input voltage (v) power train switching frequency and periodic input charge vs. input voltage - full load v out : 20 v v out : 48 v v out : 55 v 0 2 4 6 8 10 12 14 16 850 875 900 925 950 975 1000 1025 1050 35 40 45 50 55 60 65 70 75 total input charge per switching cycle (c) f sw (khz) input charge ( c) swi tching frequency (khz) figure 14 typical power train switching frequency and periodic input charge vs. v in , v out ; i out = 4.17 a 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 051015202530354045505560657075 effective capacitance (?) appli ed v ol tage (v) effec ti ve internal in put an d out put capacitan ce vs. a pplied voltage in pu t a nd ou tput capac itanc e (uf) in pu t capac ita nce only (uf) inp ut and output capacitance inp ut capa citance only figure 13 effective internal input and output capacitance vs. voltage C ceramic type input voltage (v) power train switching frequency and periodic output charge vs. input voltage - full load v out : 20 v v out : 48 v v out : 55 v 0 2 4 6 8 10 12 14 16 850 875 900 925 950 975 1000 1025 1050 35 40 45 50 55 60 65 70 75 total output charge per switching cycle (c) f sw (khz) swi tching frequency (khz) output char ge ( c) figure 15 typical power train switching frequency and periodic output charge vs. v in , v out ; i out = 4.17 a

figure 16 output power vs. share / control node voltage; v in = 48.0 v, v out = 48.0 v, t case = 25c

figure 17 typical share / control node voltage vs. t case and i out ; v in = 48.0 v, v out = 48.0 v typical performance characteristics (cont.) the following figures present typical performance at t c = 25oc, unless otherwise noted. see associated figures for general trend data.
rev 1.5 prm tm regulator page 25 of 42 11/2015 vicorpower.com 800 927.9474 PRM48AH480X200A00 load current (a) dc modulator gain and powertrain equivalent resistance vs. output current - v out = 55 v v in : 36 v v in : 48 v v in : 75 v r eq (? ) g cn (db) 0 50 100 150 200 250 300 350 400 -12 -10 -8 -6 -4 -2 0 2 4 00.511.52 2.5 3 3.5 4 r eq (?) g cn (db) figure 20 powertrain characteristics vs. i out , v in resistive load, v out = 55.0 v load current (a) dc modulator gain and powertrain equivalent resistance vs. output current - v out = 48 v v in : 36 v v in : 48 v v in : 75 v r eq (? ) g cn (db) 0 50 100 150 200 250 300 350 -8 -6 -4 -2 0 2 4 6 00.511.52 2.5 3 3.5 4 4.5 r eq (?) g cn (db) figure 19 powertrain characteristics vs. i out , v in resistive load, v out = 48.0 v load current (a) powertrain equivalent input resistance vs. output current - v out = 20 v v in : 36 v v in : 48 v v in : 75 v r in (? ) 0 20 40 60 80 100 120 140 160 00.511.52 2.5 3 3.5 4 4.5 figure 21 magnitude of powertrain dynamic input impedance vs. i out; v in ; v out = 20.0 v load current (a) powertrain equivalent input resistance vs. output current - v out = 48 v v in : 36 v v in : 48 v v in : 75 v r in (? ) 0 10 20 30 40 50 60 00.511.52 2.5 3 3.5 4 4.5 figure 22 magnitude of powertrain dynamic input impedance vs. i out; v in ; v out = 48.0 v load current (a) powertrain equivalent input resistance vs. output current - v out = 55 v v in : 36 v v in : 48 v v in : 75 v r in (? ) 0 10 20 30 40 50 60 00.511.52 2.5 3 3.5 4 figure 23 magnitude of powertrain dynamic input impedance vs. i out; v in ; v out = 55.0 v typical performance characteristics (cont.) the following figures present typical performance at t c = 25oc, unless otherwise noted. see associated figures for general trend data. load current (a) dc modulator gain and powertrain equivalent resistance vs. output current - v out = 20 v v in : 36 v v in : 48 v v in : 75 v 0 20 40 60 80 100 120 -4 -2 0 2 4 6 8 00.511.52 2.5 3 3.5 4 4.5 r eq (? ) g cn (db) r eq (?) g cn (db) figure 18 powertrain characteristics vs. i out , v in resistive load, v out = 20.0 v
rev 1.5 prm tm regulator page 26 of 42 11/2015 vicorpower.com 800 927.9474 PRM48AH480X200A00 general characteristics specifications apply over all line and load conditions, t int = 25oc and output voltage from 20.0 v to 55.0 v, unless otherwise noted. boldface specifications apply over the temperature range of -40oc < t int < 125oc (t-grade). attribute symbol conditions / notes min typ max unit mechanical length l 21.8 22.0 22.3 mm (0.86) (0.87) (0.88) in width w 16.3 16.5 16.8 mm (0.64) (0.65) (0.66) in height h 6.48 6.73 6.98 mm (0.255) (0.265) (0.275) in volume vol no heatsink 2.44 cm 3 (0.15) in 3 weight w 7 g nickel 0.51 2.03 lead finish palladium 0.02 0.15 m gold 0.003 0.050 thermal operating internal temperature t int t grade -40 125 oc m grade -55 125 oc thermal impedance int-case 2 oc/w int-lead 9 oc/w thermal capacity 5 ws / oc assembly peak compressive force supported by j-lead only 3 lbs applied to case (z-axis) 5.3 lbs / in 2 storage temperature t st t grade -40 125 oc m grade -65 125 oc esd rating hbm method per human body model test class 1c esda/jedec jds-001-2012 v cdm charged device model jesd22-c101e class 2 soldering peak temperature during re?ow msl 4 (datecode 1528 and later) 245 oc maximum time above 217 oc 60 90 s peak heating rate during re?ow 1.5 2.0 oc / s peak cooling rate post re?ow 2.5 3.0 oc / s reliability and general agency approvals telcordia issue 2 - method i case 1; ground benign, 5.28 mhrs mtbf controlled mil-hdbk-217 plus parts count - 25c ground benign, 5.29 mhrs stationary, indoors / computer pro?le agency approvals / standards c tuv us ce marked for low voltage directive and rohs recast directive, as applicable
rev 1.5 prm tm regulator page 27 of 42 11/2015 vicorpower.com 800 927.9474 PRM48AH480X200A00 pin functions +in, -in input power pins +out, -out output power pins. module cannot sink current. enable this pin turns the supply on and off. the pin is both an input and an output and can provide the following features: n delayed start: upon application of voltage (>uvlo) to the module power input and after t off , the enable pin will source a constant 90 a current. n output enable: when enable is allowed to pull up above the enable threshold, the enable pin will pull up to 5 v with 1.8 ma source capability, and the module will be enabled. n output disable: enable may be pulled down externally in order to disable the module. pull down resistance should be less than 235 to sgnd. n fault detection flag: the enable 5 v voltage source is internally turned off when a fault condition is detected . enable control should be implemented using an open collector configuration. it is not recommended to drive this pin externally. vaux: auxiliary voltage source use this pin to power external devices with a non-isolated 9v supply, with up to 5 ma load capability, switched with enable input. do not place a capacitor over 0.04 f on this pin. sgnd: signal ground this is a low current pin which provides a kelvin connection to the prms internal signal ground. use this pin as the ground reference for external circuitry and signals to avoid voltage drops caused by high currents on power returns. in array configurations, sgnd pins should be star connected at a single point. a series resistor (~1) to the star location is recommended to decouple return currents. vc: vtm control this output pin is used to temporarily provide vcc voltage to connected vtms during start up. the pulse is nominally 14 v, 10 ms wide. a vtm can self-power once its input voltage reaches its minimum specified input voltage. the prm output must be checked to make sure it reaches this threshold voltage before the vc pulse expires. trim the trim pin is used to select the operating mode and to trim the prm output when adaptive loop operating mode is selected. the trim pin has an internal pull-up to v cc_int through a 10 k resistor. operating mode select: if trim is pulled below 0.45 v during the first startup after v in is applied, remote sense / slave operation is selected. otherwise, adaptive loop operation is selected. this selection persists until v in is removed from the part, and is not changed by fault or disable events. output voltage trim: sets the output voltage of the prm in adaptive loop operation. if trim is permitted to pull up to 3.20 v or higher during start up, trim is disabled, and the output is set to the nominal of 48.0 v. if trim is held between 1.00 v to 2.75 v during start up, trim is enabled, and the output is scaled by a factor of 20 resulting in an output voltage range of 20.0 v to 55.0 v. this selection persists until the prm is restarted with the enable pin, or due to fault auto-recovery. al: adaptive loop (adaptive loop operation) this input pin allows you to set the adaptive loop load line. every volt on this pin represents 1.0 of positive output slope. there is an internal 10 k pullup resistor to v cc_int . if al is permitted to pull up to 3.20 v or higher during start up, the adaptive loop load line is disabled. this selection persists until the prm is restarted with the enable pin, or due to fault auto-recovery. vt: vtm temperature (adaptive loop operation) this pin is used in the adaptive loop compensation algorithm to account for the vtm output resistance variation as a function of temperature. the vtm tm pin provides this voltage, scaled as the temperature in k (kelvin) divided by 100, so 25c is 2.98 v. leave disconnected or pull below 1.9 v to disable. the adjustment is fixed at 0.3%/c relative to the value at 25c ref: reference (adaptive loop operation) this output pin allows you to monitor the internal reference voltage in adaptive loop operation. during normal operation it represents the output voltage scaled by a factor of 20. in adaptive loop operation this pin is for monitoring purposes only and should not be driven or loaded externally. ref_en: reference enable (remote sense operation) in remote sense operation this pin outputs a regulated 3.25 v, 4 ma voltage source. it is enabled only after successful start up of the prm powertrain. ref_en is intended to power the output current transducer and also the voltage reference for the external control loop. powering the reference generator with ref_en helps provide a controlled start up, since the output voltage of the system is able to track the reference level as it comes up. share (adaptive loop and slave operation) this bus sets the output current level for all the prm modules when operating in an array (master-slave configuration). connect them together among the modules in the shared bus. one prm should be configured as a master by connecting trim for adaptive loop operation. all other prms should be configured as slaves by pulling their respective trim pins low. this pin can be used to monitor the error voltage externally. 0 to 100% load is represented by a voltage between 0.79 v and 7.40 v. control node (remote sense operation) in remote sense operation, this is the input to the modulator which determines the powertrain timing and ultimately the module output power. an internal 0.5 ma current sink is always active. the bi- directional buffer between control node and the modulator has two states. in normal operation, control node will be above the 0.79 v switching threshold, and will drive the modulator through the buffer. an internal 7.40 v clamp determines the maximum output power that can be requested of the modulator.
when control node falls below 0.79 v, the converter will stop switching. an internal circuit clamps the modulator input to 7.40 v, and a buffer will source up to 2.5 ma out of the pin at that clamp level. for this reason, the output impedance of the amplifier driving control node must be taken into account. a rail-to-rail operational amplifier with low output impedance is always recommended. the powertrain small signal (plant) response consists of a single pole determined by the load resistance, the powertrain equivalent output resistance, and the total output capacitance (internal and external to the module). both the modulator gain and the equivalent output resistance vary as a function of line, load and output voltage. as the load increases, the powertrain pole moves to higher frequency. as a result, the closed loop crossover frequency will be the highest at full load and lowest at minimum load. figure 24 shows a reference ac small-signal model. ifb: current feedback (remote sense operation) in remote sense operation, ifb is the input for the module output overcurrent protection and current limit features. a voltage proportional to the powertrain output current must be applied to ifb in order for overcurrent protection to operate properly. if the ifb voltage exceeds the ifb pins overcurrent protection threshold, the powertrain will stop switching. if the ifb voltage falls below the overcurrent protection threshold within t blank time, then the powertrain will immediately resume switching. otherwise a fault is detected. the current limit threshold for the ifb pin is set lower than the protection threshold. when the ifb pin average voltage exceeds the current limit threshold, an internal integrator will activate a clamp amplifier which overrides the modulator input maximum level. this causes the powertrain to maintain a constant output current. the bandwidth of this current limit integrator is significantly slower than that of the control node input. therefore this current limit cannot be used in lieu of properly compensating the (external) control loop to avoid exceeding maximum current or power ratings for the device. design guidelines the prm48ah480x 200a00 regulator is specifically designed to provide a controlled factorized bus distribution voltage for powering downstream vtm transformer fast, efficient, isolated, low noise point-of-load (pol) converters. the prm48ah480x 200a00 can be configured for two operating modes depending on the type of regulation required. in adaptive loop operation the regulation circuitry is enabled within the device and regulates the voltage at the output terminals. the prm48ah480x 200a00 has a programmable adaptive loop load line which can be used to compensate for downstream vtm output resistance allowing for precise point of load regulation without the need for remote sensing. in remote sense operation, the internal regulation circuitry is disabled and the voltage regulation circuitry is provided externally allowing for remote sensing directly at the point of load. in certain applications remote sense operation can improve regulation accuracy, and allow for operating with high amounts of load capacitance and optimizing load transient response. operating mode selection the operating mode is selected through use of the trim pin. when the part is first enabled after v in is applied, the trim voltage is sampled. the trim pin has an internal pull up resistor to v cc_int , so unless external circuitry pulls the pin voltage lower, it will float up to v cc_int . if trim is pulled lower than 0.45 v during the first startup after v in is applied, the part will be configured for remote sense / slave operation, where the internal voltage regulation circuitry is disabled. in this case, for all subsequent operation the part will output a voltage dependent on the share / control node voltage provided externally (either from an external regulation circuit or master prm). to configure the part for remote sense or slave operation, connect the trim pin to sgnd. it is recommended to make this connection through a 0 jumper for troubleshooting purposes. if the sampled trim voltage is higher than 0.55 v during the first startup after v in is applied, then the part will be configured for adaptive loop operation, and the internal voltage regulation circuitry is enabled. the prm will output a voltage dependent on the trim voltage, and will remain in this mode for as long as v in is applied. to configure the part for adaptive loop operation, leave the trim pin disconnected, or apply a voltage/resistance within the specified range. the operating mode is detected during the first start up after v in is applied. this selection persists until v in is removed from the part, and is not changed by fault or disable events. changing the operating mode can only be done by removing v in . rev 1.5 prm tm regulator page 28 of 42 11/2015 vicorpower.com 800 927.9474 PRM48AH480X200A00 v cn g cn c out_int v cn + - i cn_low r cn + - r eq_out r eq_in v in + - c in_int control node output figure 24 prm48ah480x 200a00 ac small signal model
rev 1.5 prm tm regulator page 29 of 42 11/2015 vicorpower.com 800 927.9474 PRM48AH480X200A00 trim k?uv trim r = v cc int <v trim k?uv out_set uv cc int <v out_set = $;26!27>7,=287#>66*;b 9.;*=270#=*=. & $" " $" .=.,=.-*7-*=,1.- remote sense / slave operation <0.45 v< 1 k ? at application of v in when enable ?rst transitions high adaptive loop operation >0.55 v [2] >3 k ? [2] at application of v in when enable ?rst transitions high trim active 1.00 v to 2.75 v 4.32 k ? to 49.9 k ? adaptive loop operation v out = 20* v trim at every start up when trim mode trim inactive >3.20 v> 10 m ? enable transitions high v out = 48.0 v table 1 trim pin function summary [2] it is not recommended to con?gure trim with a voltage less than 1.00 v in adaptive loop operation 10 10 20 v cc int 10 k? trim micro con tro ll er v trim r trim sgnd sgnd sgnd figure 25 trim connection 0 10 20 30 40 50 60 0 10 20 30 40 50 60 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 trim pin resistor (k?) output voltage (v) tr im pin v ol tage (v) prm v out vs. v trim output voltage (v) trim pi n r esi stor (k?) unspeci?d operaon recommen ded ra nge figure 26 prm v out vs. v trim design guidelines (adaptive loop operation) in adaptive loop operation, the internal voltage control circuitry is enabled and the voltage at the output terminals is regulated. the part is nominally set to provide a fixed 48.0 v output, and the trim pin can be used to adjust the output over the range of 20.0 v to 55.0 v. when used with a vtm, the al pin provides ability to program an adaptive loop load line to compensate for the output resistance (r out ) of a downstream vtm, while the vt pin provides temperature compensation to account for changes in the vtm r out over temperature. trim mode and output trim control (adaptive loop operation) in adaptive loop operation, during any start up and after enable transitions high, the trim pin voltage is sampled to determine if trim is active or inactive. if the sampled trim voltage is higher than 3.20 v then the prm will disable trim. in this case, for all subsequent operation the output voltage will be programmed to the nominal output of 48.0 v and the trim pin will be ignored during normal operation. if the sampled trim voltage is between 1.00 v and 2.75 v then the prm will activate trim mode and it will remain in this mode as long as the prm is operating. this selection persists until the prm is restarted with the enable pin, or due to fault auto-recovery. the output as a function of v trim is defined by equation (1) for 1.00 v v trim 2.75 v, and allows for an output voltage ranging from 20.0 v to 55.0 v. the trim pin is pulled up internally to v cc_int thorough a 10 k? resistor. v trim can be actively set with a dac that is ground referenced to sgnd. v trim can be passively set by connecting a resistor, r trim , from trim to sgnd such that the voltage divider made with v cc_int and the 10 k? pull up yields the desired v trim . the formula for calculating this resistor is provided in equation (1a). v out = v trim ? 20 (1) (1a) for 1.00 v v trim 2.75 v where v out_set is the desired output voltage. the output voltage transfer function saturates for applied trim voltages above approximately 2.75 v as illustrated in figure 26 to prevent the output from being driven above its rated output voltage. when trim is set lower than 1.00 v the output voltage is not specified and stable operation is not guaranteed. when trim is enabled the voltage at this pin is sampled at 120 s intervals to determine the trim level. the output can be dynamically trimmed during normal operation, however it is not recommended to use this pin in an external analog feedback loop. refer to table 1 for a summary of the trim pin functionality and the recommended voltage/resistance that should be applied to this pin.
rev 1.5 prm tm regulator page 30 of 42 11/2015 vicorpower.com 800 927.9474 PRM48AH480X200A00 adaptive loop compensation (adaptive loop operation) a factorized power system naturally has a dc load line associated with it since the regulator stage (prm) is positioned before the isolation and voltage transformation stage (vtm) consider for a moment a factorized power system that has the following parameters: n v f = 40 v n k vtm =1/4 n r out_vtm =10 mohm @ 25c at no load the output voltage at the load will be equal to 10 v (v f ? k vtm ). with increasing load current, the output voltage at the load will drop at a rate proportional to the vtms r out . it should be noted that the r out has a positive temperature coefficient and so the dc load line changes with temperature. if the presence of this load line is acceptable for your application, then the prm can be configured by way of the trim pin alone. please refer to the trimming the output voltage section for details. in this case both the al and vt pins should be left open. if the presence of this load line is undesirable, the load line can be eliminated by way of the prms adaptive loop (al) engine. the al engine measures the output current of the prm and accordingly increases the output voltage of the prm in order to regulate the prms output resistance to a fixed negative resistance, r ll_al , settable by way of the al pin. r ll_al should be sized to exactly cancel the r out of the vtm at 25c. the al engine is also able to account for the positive temperature coefficient of r out by way of its vt pin which will be explained shortly. setting the adaptive loop load line (adaptive loop operation) to determine an appropriate value for the compensation slope (r ll_al ) it helps to reflect the vtms output resistance to the input side of the vtm. a resistance on the output side of the vtm is scaled by the vtms transformer ratio (k vtm ) squared as defined by equation (2): r llal = r out_refl =r out_vtm_25c ? ( 1 ) 2 (2) k vtm where r out_vtm is the vtm output resistance at 25c k vtm is the vtm transformer ratio v in /v out for our hypothetical vtm from above (with k vtm = 1/4 and r out_vtm = 10 m?) the output resistance reflected over to the input would be equal to 160 m?. for this example, r ll_al should be set to -160 m? to approximately cancel at 25c the inherent load line from the vtm. r ll_al is set by the voltage difference between the al pin and sgnd pin, v al , per the following formula: r ll_al = v al ? (-1.0) ?/v (3) v al 3.10 v where v al is the voltage on the al pin v al is sampled by a 10-bit adc, whose input is connected to v cc_int through a 10 k? pull up resistor. this pull up disables the al engine when the al pin is left open. v al can be actively set with a dac that is ground referenced to sgnd. v al can be passively set by connecting a resistor, r al , from al to sgnd such that the voltage divider made with v cc_int and the 10 k? pull up yields the desired v al . the formula for calculating this resistor is provided in equation (4). r al = 10 k ?v al (4) v cc_int C v al figure 28 prm-vtm adaptive loop example -3 -2 -1 0 1 2 3 0 20 40 60 80 100 output voltage %difference from nominal (%) lo ad current ( %) prm and vtm output vol tage a dap ti ve loop comensation example vt m v out (uncompensated) prm v out vt m v out (regulat ed) c ompensated vtm ou tput ad ap tive loop c ompensation brings o utput into regul ation prm output increases with load to compensate for vtm r out uncomensated vtm output decreases with load due to r out figure 27 adaptive loop compensation illustration prm enable trim share/ control node al ifb vc vt vaux ref/ ref_en +in Cn +out Cut tm vc pc v out +in Cn Cut +out adaptive loop t emperature feedback vtm start up pulse sgnd sgnd gnd sgnd r trim on/off control sgnd vf: 20 v to 55 v isolation bound ry sec_gnd vtm primary secondary c in c f c out vin l f r al
rev 1.5 prm tm regulator page 31 of 42 11/2015 vicorpower.com 800 927.9474 PRM48AH480X200A00 similar to trim, al is sampled during every start up to determine if the adaptive loop load line is enabled or disabled. if the al pin is allowed to pull up to 3.20 v or higher during start up, then the prm will disable the adaptive loop load line as long as the prm remains operating. in this case, for all subsequent operation the output voltage will be remain at the set voltage, and the al pin will be ignored. this selection persists until the prm is restarted with the enable pin, or due to fault auto-recovery. when al is enabled, the voltage at this pin is sampled at 120 s intervals to determine the load line. the load line can be adjusted during normal operation, however it is not recommended to use this pin in an external analog feedback loop. adaptive loop temperature compensation (adaptive loop operation) by connecting the vt pin of the prm to the vtms tm pin, the prm is able to monitor the internal temperature of the vtm. knowing the vtms internal temperature and the temperature coefficient of the vtms r out , which is preprogrammed into the prms microcontroller, the al engine is able to scale the nominal value of r ll_al (set by the al pin) to track the vtms r out over temperature. in this way the output resistance of the prm can be tuned to cancel the output resistance of the vtm with the addition of a single resistor across the al pin and a connection of the vtms tm pin to the prms vt pin. the vtm tm voltage is equal to the vtm internal sensed temperature in kelvin divided by 100. for a temperature range of -55c to 125c the tm voltage will range from 2.18 v to 3.98 v. the adaptive loop temperature compensation is pre-programed into the internal microcontroller and is 0.3%/c assuming the vt pin is connected to the tm pin of a compatible vtm. the tm pin has an internal pull down to sgnd, and temperature compensation is disabled for vt voltages less than 1.9 v. to disable temperature compensation, leave the vt pin unconnected and open circuit. when disabled, the temperature defaults 25c. the discussion thus far only considered the case where the al engine is used to compensate for the r out of the vtm. the al engine can be more generally used to account for distribution resistances in both the factorized bus and the vtms output distribution bus. for more information on how to apply the al engine towards this end please contact vicors applications engineering department. stability considerations and external capacitance (adaptive loop operation) in adaptive loop operation, the internal voltage regulation is enabled which has a pre-determined, fixed compensation network. the compensation is designed to be stable over a fixed set of operating and load conditions including load capacitance. besides internal output capacitors, external output capacitors also contribute to the closed loop frequency response, thus should be identified and understood, in order to maintain the control loop stability. this includes capacitance placed directly on the prm output, as well as capacitance on the output of any downstream vtm (if used) reflected to its input. figure 32 illustrates the requirements for external capacitors for both the capacitance and esr value. as shown in figure 32 (a), the maximum capacitance value of ceramic capacitor is 25 f, and the capacitance of a combination of ceramic and electrotype capacitors needs to be less than 47 f. as shown in figure 32 (b) and (c), the esr value of electrotype capacitors needs to be between 0.1 ? and 1 ?; the esr value of ceramic capacitors needs to be between 2m ? and 200 m?. figure 31 adaptive loop temperature compensation illustration v cc int al micro con tro ll er v al r al sgnd sgnd sgnd 10 k? figure 29 al connections figure 30 vt connections vt 60 .4k v tm tm v cc int micro con tro ll er sgnd sgnd 20 k? -3 -2 -1 0 1 2 3 0 20 40 60 80 100 output voltage %difference from nominal (%) lo ad current ( %) prm and vtm output vol tage adapti ve loop with te mp era tu re compensation vtm v out : 2 5 c (uncompen sa ted) vtm v out (r egula ted) vtm v out : -55 (uncompen sa ted) vtm v out : 100c (uncompen sa ted) pr m v out : 2 5 (v t = 2.9 8 v) pr m v out : -5 5 c (vt = 2.18 v) pr m v out : 10 0 c (vt = 3. 73v) c ompen sat ion s lo pe increases with temperat ure b as ed on v t feedback vtm r out increases wit h temperature compensated vtm ou tput prm output hot prm output cold prm output ambient 2.18 v to 3.98 v (-55c to 125c)
rev 1.5 prm tm regulator page 32 of 42 11/2015 vicorpower.com 800 927.9474 PRM48AH480X200A00 current limit (adaptive loop operation) in adaptive loop operation, the current limit is controlled by the internal microcontroller. the current limit approximates a brick- wall limit where the output current is prevented from crossing the current limit threshold by reducing the output voltage. the current limit threshold is pre-programmed into the internal microcontroller and cannot be changed externally. when the internal sensed current crosses the current limit threshold, the current limit will be activated after the detection time t lim_supv . once activated, the microcontroller will reduce the error amplifier reference voltage(represented by ref) in order to maintain the output current at the limit value. current limit is able to reduce the output down to v out_uvp , below which the device will shut down do to output under voltage protection. soft start timing and start up (adaptive loop operation) in adaptive loop operation, the prm has an internal soft start sequence which is initiated at every start up. this allows the prm to start into fully discharged load capacitance. the soft start sequence ramps the output by modulating the error amplifier reference voltage (ref). the result is that the prm output will rise at a controlled rate until the final voltage setpoint is reached. the total ramp time is typically 1.8 ms independent of the output trim level. this soft start ramp time is preprogrammed into the microcontroller and cannot be changed externally. load transient response (adaptive loop operation) in adaptive loop operation, response time is dependent on the internal compensation. when the adaptive loop load line is disabled, the prm output voltage will recover to the initial set value as illustrated in figure 33 and figure 34. when the adaptive loop load line is enabled, the voltage will recover to the value determined by the set point and adaptive loop load line settings as illustrated in figure 35. actual response times are model dependent and will change based on the load step magnitude, load capacitance and operating conditions. because the compensation is fixed internally the load transient response cannot be altered for adaptive loop operation. in order to improve the load transient response performance, the part can be configured for remote sense operation with an external voltage control loop optimized for the specific intended operating conditions. remote sense operation is described in the next section. figure 33 prm example 10% to 100% load transient response, adaptive loop load line disabled c el (uf) c cer (uf) c cer + c el < c cer esr (ohm) esr el esr esr (ohm) esr cer esr maxium capacitance limits (b) esr el requirements (c) esr cer requirements figure 32 output capacitance limits figure 34 prm example 100% to 10% load transient response, adaptive loop load line disabled figure 35 prm example 10% to 100% load transient response, adaptive loop load line enabled, v al = 1.20 v 25 25 47 47 22 0.1 1 0.1 1 200 2 2 200
rev 1.5 prm tm regulator page 33 of 42 11/2015 vicorpower.com 800 927.9474 PRM48AH480X200A00 arrays (adaptive loop operation) in adaptive loop operation a master-slave configuration is used for arrays. up to 5 prms of the same type may be placed in parallel to expand the power capacity of the system. one prm is designated as the master and contains the active control loop which considers control pin inputs and drives share. the other prms listen to share and act as slave powertrains only. the following high-level guidelines must be followed in order for the resultant system to start up and operate properly, and to avoid overstress or exceeding any absolute maximum ratings. n one prm must be designated as a master through configuring the trim pin voltage within the recommended range. n all other prms must be designated as slave prms by tying trim pins to sgnd. it is recommended to make this connection through a 0 jumper for troubleshooting purposes. n all prms in the array must be powered from a common power source so that the input voltage to each prm is the same. the in pins of all prms must be connected together. n an independent fuse for each prm +in connection is required to maintain safety certifications (see fusing section). n an independent inductor for each prm +in connection is recommended when used in an array, to control circulating currents among the prm inputs and reduce the impact of beat frequencies. n mismatches in both inductance, and resistance from the common power source to each prm should be minimized. n enable pins must be connected together for start up synchronization and proper fault response of the array. n share pins must be connected together to enable sharing. the bandwidth requirements of share are low enough that the bus can be considered a lumped element, rather than a transmission line, and so star connections to the master prm with stubs, as well as daisy chain connections are permitted. n the resistances between slave unit share pins and the masters should be well matched, to avoid introducing additional sharing mismatches. the share bus should not be routed under any prm. share bus parasitic capacitance to +in or +out should be minimized. n sgnd of the master prm is the reference for all control loop functions. the sgnd pins of each slave prms should be connected to the sgnd reference node on the board through a 1 resistor. n when operating within an array, the master prm is rated for full power while the slave prms are de-rated to the array rated power and current values provided for slave operation (p out_array ,i out_array ). the number of prms required to achieve a given array capacity must consider these de-ratings to avoid overstressing any prm in the array. n adaptive loop design procedures above will hold for an array, in general, although some parameters must be scaled against the number of prms in the system. arrays of more than 5 prms may be possible through use of external circuitry. please contact vicor applications for assistance with array sizing above 5 units. prm 2 slave enable trim share/ control node al ifb vt vc vaux ref/ ref_en +in Cin +out Cout sgnd 2 sgnd sgnd 2 sgnd 1 1? gnd f 2 l in 2 prm 1 master enable trim share/ control node al ifb vt vc vaux ref/ ref_en +in Cin +out Cout sgnd 1 sgnd gnd f 1 l in 1 gnd c in v in l f 2 l f 1 c f 1 vc tm pc v out +in Cin Cout +out adaptive loop t emperature feedback vtm start up pulse isolation bound ry sec_gnd vtm 1 primary secondary c out sgnd 1 r trim r al vc tm pc +in Cin Cout +out isolation bound ry vtm 2 primary secondary c f 2 vtm start up pulse sec_gnd vf: 20 v to 55 v enable bus share bus figure 36 adaptive loop array example
rev 1.5 prm tm regulator page 34 of 42 11/2015 vicorpower.com 800 927.9474 PRM48AH480X200A00 design guidelines (remote sense operation) in remote sense operation, the prm48ah480 x 200a00 is an intelligent powertrain module designed to fully exploit external output voltage feedback and current sensing sub-circuits. these two external circuits are illustrated in figure 36, which shows an example of the prm in a standalone application with local voltage feedback and high side current sensing. in general, these circuits include a precision voltage reference, an operational amplifier which provides closed loop feedback compensation, and a high side current sense circuit which includes a shunt and current sense ic. the following design procedures refer to the circuit shown in figure 36. setting the output voltage level (remote sense operation) the output voltage setpoint is a function of the voltage reference and the output voltage sense ratio. with reference to figure 36, r1 and r2 form the output voltage sensing divider which provides the scaled output voltage to the negative input of the error amplifier; a dedicated reference ic provides the reference voltage to the positive input of the error amplifier. under normal operation, the error amplifier will keep the voltages at the inverting and non-inverting inputs equal, and therefore the output voltage is defined by: (5) note that the component r1 will also factor into the compensation as described in a later section. it is important to apply proper slew rate to the reference voltage rise when the control loop is initially enabled. the recommended range for reference rise time is 1 ms to 9 ms. the lower rise time limit will ensure optimized modulator timing performance during start up, and to allow the current limit feature (through ifb pin) to fully protect the device during power-up. the upper rise time limit is needed to guarantee a sufficient factorized bus voltage is provided to any downstream vtm input before the end of the vc pulse. setting the output current limit and overcurrent protection level (remote sense operation) in remote sense operation, the internal current sensing is disabled, and an external current sense amplifier must be implemented to provide feedback to the ifb pin. the current limit and overcurrent protection set points are linked, and scale together against the current sense shunt, and the gain of the current sense amplifier. the output of the current sense ic provides the ifb voltage which has v ifb_il and v ifb_oc thresholds for the two functions respectively. the set points are therefore defined by: (6) and (7) where g cs is the gain of the current sense amplifier. 2 21 r rr vv ref out
u css il i fb il gr v i u _ cs s oc ifb oc gr v i u _ prm enable trim share/ control node al ifb vc vt vaux ref/ ref_en +in Cn +out Cut sgnd gnd sgnd on/off control sgnd c in c out v in voltage sense and error amplifier (single ended) sgnd v + vout Cn +in v C sgnd external current sense and feedback v out rs r1 r2 r3 c2 c1 voltage reference with soft start sgnd in out gnd r ss c ss 10 k sgnd v ref v ref ref 3312 figure 37 remote sense example
rev 1.5 prm tm regulator page 35 of 42 11/2015 vicorpower.com 800 927.9474 PRM48AH480X200A00 21 213 2 ? 2 1 f cc ccr p
uu u 23 2 2 1 f cr p uu 5 / load out eq load out eq c rr rr r ext out
u _ _ _ exto ut i nt o ut l oad o ut eq load o ut eq p c rr rr _ _ _ _ c ? 2 1 f
u
u u 5 1 3 mb r r log 20g 13 1z cr ? 2 1 f uu open loop gain vs. frequen cy -40 -20 0 20 40 60 80 frequency, log scale (y-intercept is application specifi c) gain (db) prm open l oop max load a b e f i j k l compensation gain c g f cmax f cmin e f f prm open l oop min load applications op-amo gbw figure 38 reference asymptotic bode plot for the considered system control loop compensation requirements (remote sense operation) in order to properly compensate the control loop, all components which contribute to the closed loop frequency response should be identified and understood. figure 24 shows the ac small signal model for the module. modulator dc gain g cn and powertrain equivalent resistance r eq_out are shown. these modeling parameters will support a design cut-off frequency up to 50khz. standard bode analysis should be used for calculating the error amplifier compensation and analyzing the closed loop stability. the recommended stability criteria are as follows: 1) phase margin > 45o: for the closed loop response, the phase should be greater than 45o where the gain crosses 0 db. 2) gain margin > 10db : the closed loop gain should be lower than - 10db where the phase crosses 0o. 3) gain slope = -20db/decade : the closed loop gain should have a slope of -20db/decade at the crossover frequency. the compensation characteristics must be selected to meet these stability criteria. refer to figure 37 for a local sense, voltage-mode control example based on the configuration in figure 36. in this example, it is assumed that the maximum crossover frequency (f cmax ) has been selected to occur between b and c. type-2 compensation (curve ijkl) is sufficient in this case. the following data must be gathered in order to proceed: n modulator gain g cn : see figures 18, 19, 20 n powertrain equivalent resistance r eq : see figures 18, 19, 20 n internal output capacitance: see figure 13 n external output capacitance value in the case of ceramic capacitors, the esr can be considered low enough to push the associated zero well above the frequency of interest. applications with high esr capacitor may require a different type of compensation, or cascade control. the system poles and zeros of the closed loop can then be defined as follows: n powertrain pole, assuming the external capacitor esr can be neglected: n main pole frequency: n compensation mid-band gain: (8) n compensation zero: (9) n compensation pole: and for f p2 >>f z1 (c 1 + c 2 c 1 ): (10)
rev 1.5 prm tm regulator page 36 of 42 11/2015 vicorpower.com 800 927.9474 PRM48AH480X200A00 midband gain design: r1, r3 (remote sense operation) with reference to figure 37: curve abc is the: n minimum output voltage in the application n maximum input voltage expected in the application n maximum load prm open loop response, and is where the maximum crossover frequency occurs. in order for the maximum crossover frequency to occur at the design choice f cmax , the compensation gain must be equal and opposite of the powertrain gain at this frequency. for stability purposes, the compensation should be in the mid-band (j-k) at the crossover. using equation (8) , the mid-band gain can be selected appropriately. compensation zero design :c1 (remote sense operation) with reference to figure 37: curve efg is the: n maximum output voltage in the application n minimum input voltage expected in the application n minimum load in the application prm open loop response, and is where the minimum crossover frequency f cmin occurs. based on stability criteria, the compensation must be in the mid-band at the minimum crossover frequency, therefore f cmin will occur where efg is equal and opposite of g mb . c1 can be selected using equation (9) so that f z1 occurs prior to f cmin . high frequency pole design: c2 (remote sense operation): using equation (10) , c2 should be selected so that f p2 is at least one decade above f cmax and prior to the gain bandwidth product of the operational amplifier (10mhz for this example). for applications with a higher desired crossover frequency the use of a high gain bandwidth product amplifier may be necessary to ensure that the real pole can be set at least one decade above the maximum crossover frequency.
rev 1.5 prm tm regulator page 37 of 42 11/2015 vicorpower.com 800 927.9474 PRM48AH480X200A00 arrays (remote sense operation) in remote sense operation up to 10 prms of the same type may be placed in parallel to expand the power capacity of the system. all prms within the array are configured for remote sense operation and are driven by an external control circuit which considers the control inputs and drives the control node bus. the following high-level guidelines must be followed in order for the resultant system to start up and operate properly, and to avoid overstress or exceeding any absolute maximum ratings. n all prms must be configured for remote sense operation by tying trim pins to sgnd. it is recommended to make this connection through a 0 ? jumper for troubleshooting purposes. n all prms in the array must be powered from a common power source so that the input voltage to each prm is the same. n an independent fuse for each prm +in connection is required to maintain safety certifications (see fusing section). n an independent inductor for each prm +in connection is recommended when used in an array, to control circulating currents among the prm inputs and reduce the impact of beat frequencies. n mismatches in both inductance, and resistance from the common power source to each prm should be minimized. n enable pins must be connected together for start up synchronization and proper fault response of the array. n reference supply to the control loop voltage reference and current sense circuitry must be enabled when all modules r ef_en pins have reached their operational voltage levels. n a single external control circuit must be implemented as described in the remote sense operation design guidelines. the control circuit should drive the control node bus. n control node pins must be connected together to enable sharing. the bandwidth requirements of control node are low enough that the bus can be considered a lumped element, rather than a transmission line, and so star connections as well as daisy chain connections are permitted. n each prm must have its own local current shunt and current sense circuitry to drive its ifb pin. n the resistances between control node pins should be well matched, to avoid introducing additional sharing mismatches. the control node bus should not be routed under any prm. parasitic capacitance to +in or +out should be minimized. n one prm should be designated to provide the sgnd reference, vaux, and ref_en voltages for the external circuitry. n the sgnd pins of each prm should be connected to the sgnd reference node on the board through a 1 ? resistor. n when operating within an array, the prms are de-rated to the array rated power and current values provided for remote sense operation (p out_array , i out_array ). the number of prms required to achieve a given array capacity must consider these de-ratings to avoid overstressing any prm in the array. n when using vaux to power external circuitry, total current draw including control node sink currents must be taken into account to ensure the maximum vaux current is not exceeded. arrays of more than 5 prms may require additional circuitry to provide the required source current. contact vicor applications engineering for more information. prm 2 enable trim share/ control node al ifb vt vc vaux ref/ ref_en +in Cin +out Cout sgnd 2 sgnd sgnd 2 sgnd 1 1? f 2 l in 2 prm 1 enable trim share/ control node al ifb vt vc vaux ref/ ref_en +in Cin +out Cout sgnd 1 sgnd f 1 l in 1 c in v in l f 2 l f 1 c f 1 vc tm pc +in Cin Cout +out vtm start up pulse isolation bound ry vtm 1 primary secondary vc tm pc +in Cin Cout +out isolation bound ry vtm 2 primary secondary c f 2 vtm start up pulse sgnd 1 v ref sgnd 1 voltage sense sgnd 1 sgnd 1 in out gnd sgnd v + vout Cin +in v C sgnd v + vout Cin +in v C c out load r ss c ss 10 k gnd gnd gnd gnd gnd control node bus enable bus figure 39 non-isolated remote sense array example [1] non-isolated con?guration: Cout connected to -in
rev 1.5 vicorpower.com prm tm regulator page 38 of 42 11/2015 800 927.9474 PRM48AH480X200A00 design guidelines (general operation) the following guidelines are general guidelines that apply to any mode of operation. fpa system considerations there are a few system level design considerations that should be carefully considered when using a prm and vtm to implement a factorized power architecture (fpa) system the vc pin of the prm should be directly connected to the vc pin of the vtm. the prm and vtm coordinate the so? start sequence of the fpa system through this connection. if the vc pins are not connected the vtm will not start up. when the prm is ready to start up, it applies a voltage on vc, which enables and powers the vtms powertrain. the prm then proceeds to ramp up its output voltage. a?er approximately 10 ms, vc returns to 0 v and the vtm can then derive power directly from the factorized bus provided that the factorized bus voltage is above the minimum speci?ed vtm operating input voltage when the vc pulse expires. all vtm faults latch the vtm powertrain o?. input power to the system as a whole must be recycled or the prm should be disabled and enabled by way of its enable pin in order to restart the system. it is recommended that the voltage on the factorized bus return to zero before the prm is re-enabled. otherwise the so? start of the system may be compromised. a rl ?lter should be placed between the prm and vtm to locally isolate switching ripple currents that can interfere with module operation. it is important that the inductance have an impedance that is much greater than that of the prm output capacitance and vtm input capacitance at the switching frequencies of the devices. a resistor should be placed in shunt to this inductor to dampen the resultant lc tank. for most cases 100 nh in parallel with 1 ? is su?cient to isolate the switching ripple currents. verifying stability a load step transient response can be used in order to estimate stability. figure 38 illustrates an example of a load step response. equation (11) can be used to predict the phase margin based on the ratio of the kick to droop (as de?ned in fig. 38). (11) burst mode operation at light loads, the prm will operate in a burst mode due to minimum timing constraints. an example burst operation waveform is illustrated in figure 39. for very light loads, and also for higher input voltages, the minimum time power switching cycle from the powertrain will exceed the power required by the load. in this case the error ampli?er will periodically drive share/conrol node below the switching threshold in order to maintain regulation. switching will cease momentarily until the error ampli?er once again drives share/control node voltage above the threshold. note that during the bursts of switching, the powertrain frequency is constant, but the number of pulses as well as the time between bursts is variable. the variability depends on many factors including input voltage, output voltages, load impedance, and error ampli?er output impedance. in burst mode, the gain of the share/control node input to the plant which is modeled in the previous sections is time varying. therefore the small signal analysis cannot be directly applied to burst mode operation. input and output ?lter design figures 14 and 15 provide the total input and output charge per cycle, as well as switching frequency, of the prm at full load under various input and output voltages conditions. figure 13 provides the e?ective internal capacitance of the module. a conservative estimate of input and output peak-peak voltage ripple at nominal line and trim is provided by equation (12): (12) q tot is the total input (fig. 14) or output (fig. 15) charge per switching cycle at full load, while c int is the module internal e?ective capacitance at the considered voltage (fig. 13) and c ext is the external e?ective capacitance at the considered voltage. v out i out d k v out i out d k time time time time (a) without adaptive loop (b) with adaptive loop figure 40 load step response example and droop vs. kick (a) without adaptive loop; (b) with adaptive loop. 2 2 2 ln ln 100 /
| 2 | 2 5\ d k d k m figure 41 light load burst mode of operation ext i nt sw fl to t cc f i q v
u < 6 4.0
rev 1.5 prm tm regulator page 39 of 42 11/2015 vicorpower.com 800 927.9474 PRM48AH480X200A00 input filter stability the prm can provide very high dynamic transients. it is therefore very important to verify that the voltage supply source as well as the interconnecting lines are stable and do not oscillate. for this purpose, the converter dynamic input impedance magnitude is provided in figures 21, 22, 23. it is recommended to provide adequate design margin with respect to the stability conditions illustrated in the previous sections. inductive source and local, external input decoupling capacitance with negligible esr (i.e.: ceramic type) the voltage source impedance can be modeled as a series r line l line circuit. the high performance ceramic decoupling capacitors will not significantly damp the network because of their low esr; therefore in order to guarantee stability the following conditions must be verified: (13) (14) it is critical that the line source impedance be at least an octave lower than the converters dynamic input resistance, 14 . however, r line cannot be made arbitrarily low otherwise equation 13 is violated and the system will show instability, due to under-damped rlc input network. inductive source and local, external input decoupling capacitance with significant r cin_ext esr (i.e.: electrolytic type) in order to simplify the analysis in this case, the voltage source impedance can be modeled as a simple inductor l line . notice that the high performance ceramic capacitors c in_int within the prm, should be included in the external electrolytic capacitance value for this purpose. the stability criteria will be: (15) (16) equation 16 shows that if the aggregate esr is too small C for example by using very high quality input capacitors (c in_ext ) C the system will be under-damped and may even become destabilized. again, an octave of design margin in satisfying 15 should be considered the minimum. layout considerations application note an:005 details board layout recommendations using vi chip? components, with details on good power connections, reducing emi, and shielding of control signals and techniques to reference them to sgnd. avoid routing control signals (enable, trim, al etc.) directly underneath the prm. it is critical that all control signals (aside from vc and vt) are referenced to sgnd, both for routing and for pull- down and bypassing purposes. vc and vt provide control and feedback from a vtm, and must be referenced to Cout of the prm (-in of the vtm). sgnd is connected to Cin internally to the prm. sgnd should not be tied to any other ground in the system. input fuse recommendations a fuse should be incorporated at the input to each prm, in series with the +in pin. a 10 a or smaller input fuse (littelfuse? nano2? 451/453 series) is required to safety agency conditions of acceptability. always ascertain and observe the safety, regulatory, or other agency specifications that apply to your specific application. thermal considerations vichip products are multi-chip modules whose temperature distribution varies greatly for each part number as well as with the input / output conditions, thermal management and environmental conditions. maintaining the top of the PRM48AH480X200A00 case to less than 100oc will keep all junctions within the vi chip module below 125oc for most applications. the percent of total heat dissipated through the top surface versus through the j-lead is entirely dependent on the particular mechanical and thermal environment. the heat dissipated through the top surface is typically 60%. the heat dissipated through the j-lead onto the pcb board surface is typically 40%. use 100% top surface dissipation when designing for a conservative cooling solution. it is not recommended to use a vi chip module for an extended period of time at full load without proper heat sinking. in eq ext in i nt in line l ine rcc l r _ _ _ ) ( u
in eq line rr _ in eq r _ ex t in cineq rr _ _ in eq c ext in line r rc l ext in _ _ _ u
rev 1.5 prm tm regulator page 40 of 42 11/2015 vicorpower.com 800 927.9474 PRM48AH480X200A00 product outline drawing and recommended land pattern
revision date description page number(s) 1.1 11/12/12 final approved data sheet for intital release n/a 1.2 02/15/13 updated format throughout all 1.3 07/25/13 updated maximum time abover 217c 26 added array diagrams 33 & 37 rev 1.5 page 41 of 42 11/2015 vicorpower.com 800 927.9474 00a002x084ha84mrp revision history 1.4 09/30/15 updated msl rating 26 1.5 11/16/15 minor changes in efficiency specifications 5 corrections to schematic labels 16
rev 1.5 prm tm regulator page 42 of 42 11/2015 vicorpower.com 800 927.9474 PRM48AH480X200A00 vicors comprehensive line of power solutions includes high density ac-dc and dc-dc modules and accessory components, fully configurable ac-dc and dc-dc power supplies, and complete custom power systems. information furnished by vicor is believed to be accurate and reliable. however, no responsibility is assumed by vicor for its use. vicor makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication. vicor reserves the right to make changes to any products, specifications, and product descriptions at any time without notice. information published by vicor has been checked and is believed to be accurate at the time it was printed; however, vicor assumes no responsibility for inaccuracies. testing and other quality controls are used to the extent vicor deems necessary to support vicors product warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. specifications are subject to change without notice. vicors standard terms and conditions all sales are subject to vicors standard terms and conditions of sale, which are available on vicors webpage or upon request. product warranty in vicors standard terms and conditions of sale, vicor warrants that its products are free from non-conformity to its standard specifications (the express limited warranty). this warranty is extended only to the original buyer for the period expiring two (2) years after the date of shipment and is not transferable. unless otherwise expressly stated in a written sales agreement signed by a duly authorized vicor signatory, vicor disclaims all representations, liabilities, and warranties of any kind (whether arising by implication or by operation of law) with respect to the products, including, without limitation, any warranties or representations as to merchantability, fitness for particular purpose, infringement of any patent, copyright, or other intellectual property right, or any other matter. this warranty does not extend to products subjected to misuse, accident, or improper application, maintenance, or storage. vicor shall not be liable for collateral or consequential damage. vicor disclaims any and all liability arising out of the application or use of any product or circuit and assumes no liability for applications assistance or buyer product design. buyers are responsible for their products and applications using vicor products and components. prior to using or distributing any products that include vicor components, buyers should provide adequate design, testing and operating safeguards. vicor will repair or replace defective products in accordance with its own best judgment. for service under this warranty, the buyer must contact vicor to obtain a return material authorization (rma) number and shipping instructions. products returned without prior authorization will be returned to the buyer. the buyer will pay all charges incurred in returning the product to the factory. vicor will pay all reshipment charges if the product was defective within the terms of this warranty. life support policy vicors products are not authorized for use as critical components in life support devices or systems without the express prior written approval of the chief executive officer and general counsel of vicor corporation. as used herein, life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. a critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. per vicor terms and conditions of sale, the user of vicor products and components in life support applications assumes all risks of such use and indemnifies vicor against all liability and damages. intellectual property notice vicor and its subsidiaries own intellectual property (including issued u.s. and foreign patents and pending patent applications) relating to the products described in this data sheet. no license, whether express, implied, or arising by estoppel or otherwise, to any intellectual property rights is granted by this document. interested parties should contact vicor's intellectual property department. the products described on this data sheet are protected by the following u.s. patents numbers: 5,945,130; 6,403,009; 6,710,257; 6,788,033; 6,940,013; 6,969,909; 7,038,917; 7,154,250; 7,166,898; 7,187,263; 7,202,646; 7,361,844; 7,368,957; re40,072; d496,906; d506,438; d509,472; and for use under 6,975,098 and 6,984,965. vicor corporation 25 frontage road andover, ma, usa 01810 tel: 800-735-6200 fax: 978-475-6715 email customer service: custserv@vicorpower.com technical support: apps@vicorpower.com

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